Semiconductor device and manufacturing method therefor

ABSTRACT

The present invention relates to a semiconductor device, including: a first channel layer, which includes a first channel region, a first gate doped region, and a second channel region, where the second channel region is located above the first channel region, and the first gate doped region is located between the first channel region and the second channel region; a first barrier layer, where a first heterojunction having a vertical interface is formed between the first channel layer and the first barrier layer, and a vertical 2DEG or 2DHG is formed in the first heterojunction; a first electrode, which is located below the first gate doped region and in electric contact with the 2DEG or 2DHG in the first heterojunction; a second electrode, which is located above the first gate doped region and in electric contact with the 2DEG or 2DHG in the first heterojunction; and a third electrode, which is in electric contact, in the first gate doped region, with the 2DEG or 2DHG in the first heterojunction. The present invention further includes a manufacturing method for a semiconductor device.

TECHNICAL FIELD

The present invention relates to a semiconductor device, and inparticular, to nitride semiconductor device.

BACKGROUND

Group III Nitride semiconductors are important semiconductor materials,and mainly includes AlN, GaN, and InN, as well as compounds of thesematerials, such as AlGaN, InGaN, and AlInGaN. Due to advantages such asdirect band gap, wide forbidden band and high breakdown electric fieldintensity, group III nitride semiconductors represented by GaN havebroad application prospects in the fields such as light-emittingdevices, power electronics and radio frequency devices.

Unlike conventional non-polar semiconductor materials such as Si, thegroup III nitride semiconductors have polarity. In other words, they arepolar semiconductor materials. Polar semiconductors have many uniqueproperties. Particularly importantly, fixed polarized charges arepresent at a surface of the polar semiconductor or at an interface oftwo different polar semiconductors. These fixed polarized charges mayattract movable electron or hole carriers and thus form two-dimensionalelectron gas (2DEG) or two-dimensional hole gas (2DHG). The generationof 2DEG or 2DHG neither requires an additional electric field, nordepends on a doping effect in the semiconductor. It is spontaneouslygenerated. The 2DEG or 2DHG at the interface of the polar semiconductorsmay have a high surface charge density. Meanwhile, without doping, the2DEG or the 2DHG has high mobility because of reduction of ionscattering effect and so on that the 2DEG or the 2DHG is usuallysubjected to undertake. The high density of the surface charge and highmobility enable the 2DEG or 2DHG spontaneously generated at thoseinterfaces to have good conductivity and high response speed.

In combination with inherent advantages of the nitride semiconductorssuch as high breakdown electric field, the 2DEG or 2DHG may be used tomanufacture high mobility transistors. The performance in high energy,high voltage or high frequency applications is significantly better thanthe conventional Si or GaAs devices. However, existing structures havemany defects, which seriously restrict the application ranges.

SUMMARY

With regard to the technical problems in the prior art, the presentinvention provides a semiconductor device, including:

BRIEF DESCRIPTION OF THE DRAWINGS

The preferred embodiments of the present invention will be furtherdescribed below with reference to the accompanying drawings.

FIG. 1A is a sectional view of a single-channel HEMT according to anembodiment of the present invention.

FIG. 1B is a schematic structural diagram of an electric field of adevice having a body electrode and complementary channels in an on stateaccording to an embodiment of the present invention.

FIG. 1C is a schematic structural diagram of an electric field of adevice having a body electrode and complementary channels when thecomplementary channels are in an off state according to an embodiment ofthe present invention.

FIG. 2 is a sectional view of a dual-channel HEMT according to anembodiment of the present invention.

FIG. 3 is a sectional view of a single-channel HHMT according to anembodiment of the present invention.

FIG. 4 is a sectional view of a dual-channel HHMT according to anembodiment of the present invention.

FIG. 5A to FIG. 5Z are schematic flowcharts of a manufacturing methodfor a dual-channel HEMT according to an embodiment of the presentinvention.

DETAILED DESCRIPTION

To make the objectives, technical solutions, and advantages of thepresent invention clearer, the following clearly and completelydescribes the technical solutions in the embodiments of the presentinvention with reference to the accompanying drawings in the embodimentsof the present invention. Apparently, the described embodiments aremerely some rather than all of the embodiments of the present invention.All other embodiments obtained by persons of ordinary skill in the artbased on the embodiments of the present invention without creativeefforts fall within the scope of protection of the present invention.

In the following detailed description, reference may be made to variousdrawings which constitute a part of the present application and serve toexplain specific embodiments of the present application. In thedrawings, similar reference signs denote substantially similarcomponents in different figures. The individual specific embodiments ofthe present application will be described in sufficient detail below toenable persons of ordinary knowledge and skills in the art to carry outthe technical solutions of the present application. It is understoodthat other embodiments may be utilized, or structural, logical orelectrical changes may be made to the embodiments of the presentapplication.

The present invention provides a semiconductor device. In someembodiments, the semiconductor device may be formed on a foreignsubstrate. For example, by using a nucleation layer as a medium, usageof an expensive native substrate is avoided, a distance between avertical heterojunction and a foreign substrate is increased, and thusthe voltage withstanding of the semiconductor device is improved.Furthermore, in some embodiments, the foreign substrate can be removed,and thus the performance of the semiconductor device is furtherimproved. The foreign substrate is a substrate other than a GaNintrinsic semiconductor, and includes, but is not limited to, a siliconSi substrate, a sapphire (Al₂O₃), and a silicon carbide SiC substrate,

In the present application, involved carriers are electrons or holes. Aninvolved doping type is an N type or a P type, and conductive majoritycarriers are also electrons or holes. Therefore, describing a situationthat the carriers and the doped majority carriers are the same oropposite as the carrier type and the doping type being the same oropposite could be understood by a person skilled in the art. Inaddition, the description about electric contact in the presentapplication not only includes a direct or indirect electrical connectionrelationship, but includes an electrical interaction relationship.

In the present application, P-type doping is usually doping a nitridesemiconductor with elements such as Mg and Zn, and N-type doping isusually doping a nitride semiconductor with elements such as Si, O, Seand Ge.

The semiconductor device provided by the present invention may be aSchottky diode, an HEMT, an HHMT, or other semiconductor devices. Thefollowing takes an HEMT as an example for description. A person skilledin the art should understand that a Schottky diode can also beimplemented by using a similar mode.

FIG. 1A is a sectional view of a single-channel HEMT according to anembodiment of the present invention. As shown in FIG. 1A, an HEMT 100includes: a first channel layer 103 and a first barrier layer 104A. Afirst heterojunction having a vertical interface is formed between thefirst channel layer 103 and the first barrier layer 104A, and a vertical2DEG 105A is formed in the first heterojunction.

In some embodiments, the first channel layer 103 includes a firstchannel region 132, a first gate doped region 134, and a second channelregion 135. The first channel region 132 is an N-type doping regionbased on a nitride semiconductor (e.g., GaN). The doping is usually lowdoping or non-(intentional) adulteration, and the doping concentrationis lower than 1E17/cm³. Low doping or non-doping in the first channelregion 132 can reduce a channel carrier mobility reduction phenomenoncaused by overall doping of the device.

The first gate doped region 134 is located above the first channelregion 132. The first gate doped region 134 is a P-type doping regionbased on a nitride semiconductor (e.g., GaN). A majority carrier type inthe first gate doped region 134 is opposite to a device carrier type.Based on the doping concentration of the first gate doped region, thefirst gate doped region 134 can deplete two-dimensional carriers (i.e.,2DEG) in the HEMT 100, implementing a normally off state of the deviceunder a non-operating state (no voltage applied). Generally, the dopingconcentration of the first gate doped region 134 is 1E18-1E20/cm³. Insome embodiments, the HEMT 100 has different threshold voltages due todifferent doping concentrations of the first gate doped region 134.Therefore, the doping concentration of the first gate doped region 134also has a function of modulating the threshold voltage of the device.

The second channel region 135 is disposed above the first gate dopedregion 134. The second channel region 135 is an N-type doping regionbased on a nitride semiconductor (e.g., GaN). Low doping ornon-(intentional) doping in the second channel region 135 can reduce achannel carrier mobility reduction phenomenon caused by overall dopingof the device.

The first channel region 132, the first gate doped region 134, and thesecond channel region 135 are all components of the first channel layer103, and each region is formed on the basis of a same nitridesemiconductor or a nitride semiconductor having a similar forbidden bandgap. Therefore, the forbidden band gap of the first channel layer 103,as the entirety of the channel layer, is uniform. In some embodiments,the first channel layer 103 further includes other regions formed on thebasis of the same nitride semiconductor or a nitride semiconductorhaving a similar forbidden band gap. Furthermore, because the regionshave the same or similar forbidden band gaps, electrical characteristicsof transition parts between the regions are relatively stable, and haveno adverse effect on the overall device performance.

In some embodiments, the first channel layer 103 is defined by a trench.A trench is first formed before the first channel layer 103 is formed.The height, width and other measures of the trench are the same as orsimilar to the height, width and other measures of a desired firstchannel layer. However, the first channel layer 103 is epitaxially grownin the trench. The first channel layer 103 formed in this mode has agreater aspect ratio, and epitaxial growing conditions and themorphology of the channel layer are more easily controlled.

As shown in FIG. 1A, the first barrier layer 104A is disposed at theright side of the first channel layer 103. The first heterojunctionhaving the vertical interface is formed between the first channel layer103 and the first barrier layer 104A, and the vertical 2DEG 105A isformed in the first heterojunction. Here, carriers of the 2DEG 105A areelectrons. Moreover, doping types of the first channel region 132 andthe second channel region 135 are the N type, and can also provideelectrons. Therefore, is can be considered that the doping types of thefirst channel region 132 and the second channel region 135 are the sameas a two-dimensional carrier type. Similarly, a doping type of the firstgate doped region 134 is opposite to the two-dimensional carrier type.

Under normal growth conditions, surfaces of a channel layer and abarrier layer grown on a Si (111) surface are <0001> surfaces. That isto say, a direction from the Si substrate to the channel layer and thebarrier layer is a <0001> crystal orientation. Under this crystalorientation, 2DEG is obtained at an interface close to the channel layerand the barrier layer in the channel layer. If the crystal orientationis opposite, i.e., a <000-1> direction, 2DHG is obtained at theinterface close to the channel layer and the barrier layer in thechannel layer.

In some embodiments, the first channel layer 103 and the first barrierlayer 104A may be formed above the substrate and the nucleation layer(not shown). After this, the substrate and the nucleation layer areremoved. In this way, a structure of a final device does not include thesubstrate and the nucleation layer, facilitating elimination of effectsbrought by a foreign substrate (for example, Si).

As shown in FIG. 1A, in the present embodiment, the HEMT 100 furtherincludes: a first electrode 107 and a second electrode 108. The firstelectrode 107 is located below the first gate doped region 134 and inelectric contact with the 2DEG 105A in the first heterojunction. Thesecond electrode 108 is located above the first gate doped region 134and also in electric contact with the 2DEG 105A in the firstheterojunction. The first electrode 107 and the second electrode 108 maybecome a drain and a source of the HEMT 100. In the present embodiment,the first electrode 107 and the second electrode 108 are in ohmiccontact with the channel layer and/or barrier layer 104A. As understoodby a person skilled in the art, the electric contact here not onlyincludes a direct or indirect electrical connection relationship, butincludes an electrical interaction relationship.

As shown in FIG. 1A, the HEMT 100 further includes a third electrode109. The third electrode 109 is in electric contact, in the first gatedoped region 134, with the 2DEG 105A in the first heterojunction. Thethird electrode 109 is provided between the first electrode 107 and thesecond electrode 108, and can serve as a gate, controlling currentintensity between the first electrode 107 and the second electrode 108,to form a HEMT structure. For example, a voltage applied to the thirdelectrode 109 can be modulated as majority carriers (holes) in the firstgate doped region 134. Under this effect, the carriers (electrons) inthe 2DEG 105A are not in a depletion state, and a conductive channel isformed between the first electrode 107 and the second electrode 108again. In some embodiments, a horizontal extending length of the thirdelectrode 109 is not less than a length of the 2DEG 105A, to implementcontrol on a current path between the first electrode 107 and the secondelectrode 108. Preferably, when the first electrode 107 serves as thedrain to be connected to a high voltage, the third electrode 109 islocated between the first electrode 107 and the second electrode 108,and is closer to the second electrode 108 which serves as the source.This configuration increases a distance between the drain and the gate,and can effectively improves the voltage withstanding of thesemiconductor device 100.

In some embodiments, the first channel layer 103 further includes afirst electric field modulation doped region 133. The first electricfield modulation doped region 133 is located near the third electrode,and electrically connected to the first gate doped region 134. As shownin FIG. 1A, the first electric field modulation doped region 133 isdisposed between the first gate doped region 134 and the first electrode107, and is closer to the first gate doped region 134. The firstelectric field modulation doped region 133 is also a P-type dopingregion based on a nitride semiconductor (e.g., GaN). The dopingconcentration is less than that of the first gate doped region 134, andis generally less than 2E19/cm³.

Therefore, the first gate doped region 134 needs to deplete allelectrons in the 2DEG 105A, and therefore, the doping concentrationthereof is relatively high. When the first electrode 107 (drain) isconnected to a high voltage, local electric field intensity at a contactposition between the first gate doped region 134 and the channel region132 is not uniform, which affects the voltage withstanding of thedevice. The first electric field modulation doped region 133therebetween, as a buffer, can avoid the problem above. Although thefirst electric field modulation doped region 133 is also P-type doped,compared with the first gate doped region 134, the doping concentrationis lower, such that the electric field modulation doped region 134 isprevented from severely depleting the channel carrier concentration,which increases the on-resistance of the device. Hence, the electricfield modulation doped region 133 adjusts electric field distribution ofthe device, reduces the local electric field intensity near the gatedoped region 134, and avoids a breakdown phenomenon caused by anexcessively high local electric field. Moreover, processing is alsofacilitated in process by first forming the first electric fieldmodulation doped region 133 and then forming the first gate doped region134 on the channel region 132.

In some embodiments, the first channel layer 103 further includes afirst ohmic contact doped region 131. The first ohmic contact dopedregion 131 is located between the first channel region 132 and the firstelectrode 107. The first ohmic contact doped region 131 is configured toform ohmic contact with the first electrode 107. A doping type of thefirst ohmic contact doped region 131 is N-type, and the dopingconcentration of the first ohmic contact doped region 131 is1E16-2E19/cm³. The first ohmic contact doped region 131 increases theconcentration of carriers, and can reduce ohmic contact resistance withthe first electrode 107.

In some embodiments, the first channel layer 103 further includes asecond ohmic contact doped region 136. The second ohmic contact dopedregion 136 is located between the second channel region 135 and thesecond electrode 108. The second ohmic contact doped region 136 isconfigured to form ohmic contact with the second electrode 108. A dopingtype of the second ohmic contact doped region 136 is N-type, and thedoping concentration of the second ohmic contact doped region 136 is1E16-2E19/cm³. The second ohmic contact doped region 136 increases theconcentration of carriers, and can reduce ohmic contact resistance withthe second electrode 108.

In some embodiments, the HEMT 100 further includes a second barrierlayer 104B, which is formed at the left side of the first channel layer103, where a second heterojunction having a vertical interface is formedbetween the first channel layer 103 and the second barrier layer 104B,and a vertical 2DHG 105B is formed in the second heterojunction. Thesecond barrier layer 104B may be made of a same nitride semiconductormaterial as the first barrier layer 104A.

The 2DEG 105A and the 2DHG 105B form complementary channels. Forexample, when the HEMT 100 is in an off state, the 2DEG 105A is close tothe first electrode 107 and at high potential, the 2DEG of the firstgate doped region 134 and the first electrode 107 is depleted, and abackground positive charge is exposed. An electric field having acertain direction is formed inside the HEMT 100, such that the electricfield distribution inside the HEMT 100 is not uniform, and thus thedevice performance is affected. The 2DHG 105B is not connected to otherelectrodes, and the non-uniform electric field distribution inside theHEMT 100 causes the distribution of the 2DHG to change, making theelectric field distribution inside the HEMT 100 more uniform, such thatthe device works more stably. A person skilled in the art shouldunderstand that the 2DHG 105B can be formed at one side of all or someregions of the first channel layer 103, such that the regions all have afunction of regulating an internal electric field. In particular, the2DHG may form a region of the first channel layer 103 corresponding to aposition between the first electrode (drain) and the third electrode(gate) (e.g., the first ohmic contact doped region 131, the firstchannel region 132, the electric field modulation doped region 133, andthe first gate doped region 134), so as to improve the voltagewithstanding of the device.

In some embodiments, also included is a fourth electrode 106, which isdisposed at a position near the first gate doped region 134, andelectrically connected to the first gate doped region 134. When there isno second heterojunction and 2DHG 105B, the fourth electrode 106 isdirectly or indirectly in electric contact with the first gate dopedregion 134. Or, as shown in FIG. 1A, the fourth electrode 106 is locatedat the position of the first gate doped region 134 and in electriccontact with the 2DHG 105B in the second heterojunction. The fourthelectrode 106 may be controlled independently as a body electrode, ormay be electrically connected to the second electrode 108. Asexemplified, the fourth electrode 106 may optionally be connected to a 0V voltage.

When the HEMT 100 works, the electrode 109 is connected to an externalvoltage to start the device. When the electrode 109 is connected to theexternal voltage, charges introduced by connecting to an externalvoltage cannot be fully released, and partial residual charges may beformed in the first gate doped region 134. These residual chargesneutralize the majority carriers in the first gate doped region 134 to acertain extent. Therefore, when the HEMT 100 works again, the thresholdvoltage of the HEMT 100 may drift. After the fourth electrode 106 isadded, when the HEMT 100 is turned off, the residual charges areconducted outside the device by means of the fourth electrode (bodyelectrode). Therefore, the potential of the first gate doped region 134is relatively fixed, and the threshold voltage of the HEMT 100 is alsomore stable.

A balance adjusting function of the complementary channels and thefourth electrode on the electric field inside the device is described indetail below in combination with FIG. 1B and FIG. 1C. In order tofacilitate simplifying the device structure, a person skilled in the artshould know that the technical effect is applicable to a device havingthe structure. FIG. 1B is a schematic structural diagram of an electricfield of a device having a body electrode and complementary channels inan on state according to an embodiment of the present invention. FIG. 1Cis a schematic structural diagram of an electric field of a devicehaving a body electrode and complementary channels when thecomplementary channels are in an off state according to an embodiment ofthe present invention. A structure same as or similar to that in FIG. 1Ais not repeated here.

FIG. 1B further includes a background positive charge 155A correspondingto the 2DEG 105A and a background negative charge 155B corresponding tothe 2DHG 105B. As shown in FIG. 1B, when the device is turned on, theelectric field inside the device is uniformly distributed, and thefourth electrode 106 basically has no effect. In the structure involvedin the present application, the electric field distribution when thedevice is in an off state is as shown in FIG. 1C. When the 2DHG 105B andthe fourth electrode 106 (body electrode) exist simultaneously, thefourth electrode 106 is located at the left side of the 2DHG 105B, andelectrically connected to the 2DHG 105B. When the device is in the offstate, the 2DHG 105B makes contact by means of the fourth electrode 106.Because the voltage of the fourth electrode 106 is far lower than thevoltage of the first electrode 107, the 2DHG 105B is fully or partiallydepleted, and the background negative charge is exposed. The backgroundnegative charge on the left side and the background positive charge onthe right side form a stable internal electric field, which isdistributed more uniformly, such that the device works more stably.

In some embodiments, the HEMT 100 further includes a first nucleationlayer. The first channel layer 103 is epitaxially grown from the firstnucleation layer. In some embodiments, the first channel layer 103 islocated above the first nucleation layer. In some embodiments, the firstnucleation layer is doped, and therefore has good conductivity. In someembodiments, the first nucleation layer is epitaxially grown from thefirst vertical interface of the substrate.

In some embodiments, an insulating layer 112 is included between theelectrode 107 and the electrode 109 at the side surfaces of the barrierlayer 104A. The insulating layer 112 extends horizontally, and amaterial thereof may be an insulating material such as SiO₂. In someembodiments, the shielding layer 112 may be a gate insulating layer, andis partially filled between the barrier layer 104A and the electrode109.

In some embodiments, the insulating layer 113 is included below theelectrode 106 at the side surface of the barrier layer 104B. Theinsulating layer 113 extends horizontally, and a material thereof may bean insulating material such as SiO₂. The shielding layer 112 and theinsulating layer 113 isolate the side surfaces of the barrier layer 104Aand the barrier layer 104B from the outside, capable of preventing theoutside from affecting the device performance.

In some embodiments, a passivation layer (not shown) may be includedabove the semiconductor device shown in FIG. 1A for protecting thesemiconductor structure below. Furthermore, a first conductorinterconnecting layer, a second conductor interconnecting layer and athird conductor interconnecting layer are further included above thesemiconductor device, and are electrically connected to the firstelectrode 107, the second electrode 108 and the third electrode 109,respectively. These are all well known by a person skilled in the artand is not repeated here. In some embodiments, the fourth electrode iselectrically connected, on the outside, to a fourth conductorinterconnecting layer above the semiconductor device. The fourthelectrodes respectively correspond to respective conductorinterconnecting layers, and have different connection positions in thevertical direction. The process is simpler.

In some embodiments, the HEMT 100 further includes a foreign substrate.In the present embodiment, the substrate is a silicon Si substrate. Thelattice of the vertical surface of the substrate has hexagonal symmetry,such that a nitride semiconductor crystal can then be epitaxially grown.For example, an exposed vertical interface of the substrate may be a Si(111) surface. In some other embodiments, the substrate may also be asapphire Al₂O₃ substrate, a SiC substrate, or a GaN intrinsic substrate.In some embodiments, the nucleation layer may be AlN. Here, thenucleation layer may also include a buffer layer (not shown). The bufferlayer may have a single-layer or multilayer structure, and includes oneor more of AIN, GaN, AlGaN, InGaN, AlInN and AlGaInN.

As known by a person skilled in the art, the foregoing descriptionmerely exemplarily describes the HEMT structure. There are many otherstructures or improvements, changes, or modifications on thosestructures for the devices involved in the present application toprovide different properties or functions. Those structures andimprovements, changes, or modifications on them are within the scope oftechnical concept of the present invention and may be also applied inthe technical solutions of the present invention.

The semiconductor device involved in the present invention, comparedwith a conventional device, includes 2DEG having the vertical structure,and the components of the channel layer of the semiconductor device arenot made of a single material, but are formed by means of differentdoping in a plurality of regions. The doping type of the gate dopedregion is opposite to the carrier type, and the carriers can bedepleted, such that the device can implement a normally off state undera normal condition that no voltage is applied to the gate. Aconventional device does not have a similar structure, and therefore isin a normally on state. Power consumption is greatly increased inpractical application.

The semiconductor device involved in the present invention does notincludes structures such as a substrate and a nucleation layer. However,the formation process is carried out on a foreign substrate, e.g., Si.The process cost is relatively low. After the device is formed, thesubstrate and the nucleation layer are removed, avoiding defects such aslow voltage withstanding of the foreign substrate. Compared withconventional devices, the formed device has better voltage withstandingand carrier mobility.

The present invention further includes a dual-channel HEMT structure.FIG. 2 is a sectional view of a dual-channel HEMT according to anembodiment of the present invention. The HEMT 200 shown in FIG. 2 mayalso be considered to be composed of two semiconductor devices HEMT 100as shown in FIG. 1 , where parts similar to the foregoing structure isnot repeated here.

As shown in FIG. 2 , the HEMT 200 includes, on the left side, a firstchannel layer 203A, which includes a first ohmic contact doped region231A, a first channel region 232A, a first electric field modulationdoped region 233A, a first gate doped region 234A, a second channelregion 235A and a second ohmic contact doped region 236A which arestacked from bottom to top. The HEMT 200 includes, on the right side, asecond channel layer 203B, which includes a third ohmic contact dopedregion 231B, a third channel region 232B, a second electric fieldmodulation doped region 233B, a second gate doped region 234B, a fourthchannel region 235B and a fourth ohmic contact doped region 236B whichare stacked from bottom to top.

The right side of the first channel layer 203A of the HEMT 200 furtherincludes a first barrier layer 204A, and the left side of the secondchannel layer 203B further includes a third barrier layer 204C. Becausethe first channel layer 203A has different energy band gaps with thefirst and second barrier layers 204A and 204C, a first heterojunctionand a third heterojunction both having a vertical interface are formedin the HEMT 200, and vertical 2DEG 205A and 2DEG 205C are formed in thetwo heterojunctions.

The ohmic contact doped region 236A and the ohmic contact doped region236B are respectively provided with an electrode 208A and an electrode208B, which are respectively in ohmic contact with the ohmic contactdoped region 236A and the ohmic contact doped region 236B, andelectrically connected to the 2DEG 205A and the 2DEG 205C. In the HEMT200, the 2DEG 205A and the 2DEG 205C in the two channel layers arerespectively formed to the right side and to the left side of thechannel layers because in the formation process, substrate verticalinterfaces for growing the structures of the two parts are arranged in asame crystal orientation structure and opposite to each other. Thisstructure can achieve a higher integration level.

The left side of the first channel layer 203A of the HEMT 200 furtherincludes a second barrier layer 204B, and the right side of the secondchannel layer 203B further includes a fourth barrier layer 204D. Becausethe channel layer has different energy band gaps with the barrier layers204B and 204D, a second heterojunction and a fourth heterojunction bothhaving a vertical interface are formed in the HEMT 200. Vertical 2DHG205B and 2DHG 205D are formed in the two heterojunctions.

In some embodiments, a fourth electrode 206A is further disposed at aposition on the left side of the second barrier layer 204B of the HEMT200 and close to the gate doped region 234A, and the fourth electrode206A is in electric contact with the 2DHG 205B in the heterojunction inthe first gate doped region 234A. A fourth electrode 206B is furtherdisposed at a position on the right side of the second barrier layer204D of the HEMT 200 and close to the gate doped region 234B, and thefourth electrode 206B is in electric contact with the 2DHG 205C in theheterojunction in the first gate doped region 234B. The fourthelectrodes 206A and 206B may be controlled independently as bodyelectrodes, or may be electrically connected to the second electrodes208A and 208B. Optionally, the fourth electrodes 206A and 206B areconnected to a 0 V voltage.

In the HEMT 200, for the first channel layer 203A and the second channellayer 203B, an electrode 209 is shared as a gate, and an electrode 207is shared as a drain. In some embodiments, the first channel layer andthe second channel layer have respective gates and drains.

In the present embodiment, the HEMT 200 not only has advantages of theHEMT 100, but the HEMT 200 also includes two conductive channels, i.e.,2DEG 205A and 2DEG 205C. The added conductive channel can increase anon-state current, and thus achieves higher power. Moreover, comparedwith the single conductive channel, the voltage withstanding and heatresistance of double conductive channels are also better. Moreover,electrodes having the same properties of a dual-conductive channelstructure can be shared, and there is no need to form two electrodes,such that the space is saved, and manufacturing cost and manufacturingtime are obviously saved.

In some embodiments, a high hole mobility transistor (HHMT) having 2DHGmay also be formed by a similar structure. FIG. 3 is a sectional view ofa single-channel HHMT according to an embodiment of the presentinvention. The part having a similar structure to that in FIG. 1 is notrepeated here.

As shown in FIG. 3 , the entire structure of a HHMT 300 is similar tothat of the HEMT 100, but because a vertical interface of a substrate ofa (000-1) surface in the formation process, which is different from thatof the HEMT 100, a conductive channel in the HHMT 300 is 2DHG 305A.Accordingly, the HHMT 300 further includes 2DEG 305B. Because theconductive channel is 2DHG 105A, carriers thereof are also changed fromelectrons to holes. Therefore, doping types of an ohmic contact dopedregion 331, a channel region 332, a channel region 335, and an ohmiccontact doped region 336 in the HHMT 300 are P type. Doping types of anelectric field modulation doped region 333 and a gate doped region 334are N type.

In the present embodiment, the HHMT does not have a substrate and anucleation layer, which do not affect the conductive channel, and thusthe performance of the device is further improved.

FIG. 4 is a sectional view of a dual-channel HHMT according to anotherembodiment of the present invention. A HHMT 400 shown in FIG. 4 may alsobe considered to be composed of two semiconductor devices HHMT 300 asshown in FIG. 3 , where parts similar to the foregoing structure is notrepeated here.

As shown in FIG. 4 , the HHMT 400 includes, on the left side, a firstchannel layer 403A, which includes a first ohmic contact doped region431A, a first channel region 432A, a first electric field modulationdoped region 433A, a first gate doped region 434A, a second channelregion 435A and a second ohmic contact doped region 436A which arestacked from bottom to top. The HHMT 400 includes, on the right side, asecond channel layer, which includes a third ohmic contact doped region431B, a third channel region 432B, a second electric field modulationdoped region 433B, a second gate doped region 434B, a fourth channelregion 435B and a fourth ohmic contact doped region 436B which arestacked from bottom to top.

The right side of the first channel layer 403A of the HHMT 400 furtherincludes a first barrier layer 404A, and the left side of the secondchannel layer 403B further includes a third barrier layer 404C. Becausethe channel layer has different energy band gaps with the barrier layers404A and 404C, a first heterojunction and a third heterojunction bothhaving a vertical interface are formed in the HHMT 200. Vertical 2DHG405A and 2DHG 405C are formed in the two heterojunctions.

The ohmic contact doped region 436A and the ohmic contact doped region436B are respectively provided with an electrode 408A and an electrode408B, which are respectively in ohmic contact with the ohmic contactdoped region 436A and the ohmic contact doped region 436B, andelectrically connected to the 2DHG 405A and the 2DHG 405C.

The left side of the first channel layer 403A of the HEMT 400 furtherincludes a second barrier layer 404B, and the right side of the secondchannel layer 403B further includes a fourth barrier layer 404D. Becausethe channel layer has different energy band gaps with the barrier layers404B and 404D, a second heterojunction and a fourth heterojunction bothhaving a vertical interface are formed in the HEMT 400. Vertical 2DHG405B and 2DHG 405D are formed in the two heterojunctions.

In some embodiments, an electrode 406A is further disposed at a positionon the left side of the second barrier layer 404B of the HHMT 400 andclose to the gate doped region 434A, and the electrode 406A is inelectric contact with the 2DHG 405B in the heterojunction in the firstgate doped region 434A. An electrode 406B is further disposed at aposition on the right side of the second barrier layer 404D of the HHMT400 and close to the gate doped region 434B, and the electrode 206B isin electric contact with the 2DHG 405C in the heterojunction in thefirst gate doped region 434B. The electrodes 406A and 406B may becontrolled independently as body electrodes, or may be electricallyconnected to the electrodes 408A and 408B. Optionally, the electrodes406A and 406B are connected to a 0 V voltage.

In the HEMT 400, for the first channel layer 403A and the second channellayer 403B, an electrode 409 is shared as a gate, and an electrode 407is shared as a drain. In some embodiments, the first channel layer andthe second channel layer have respective gates and drains.

In the present embodiment, the HEMT 400 includes two conductivechannels, i.e., 2DHG 405A and 2DHG 405C. The added conductive channelcan increase an on-state current, and thus achieves higher power.Moreover, compared with the single conductive channel, the voltagewithstanding and heat resistance of double conductive channels are alsobetter. Moreover, electrodes having the same properties of adual-conductive channel structure can be shared, and there is no need toform two electrodes, such that the space is saved, and manufacturingcost and manufacturing time are obviously saved.

The present invention further includes a manufacturing method for asemiconductor device. A manufacturing method for a semiconductor deviceof the present invention is described below by taking a manufacturingprocess for a dual-channel HEMT as an example.

FIG. 5A to FIG. 5Z are schematic flowcharts of a manufacturing methodfor a dual-channel HEMT according to an embodiment of the presentinvention. In the present embodiment, a semiconductor device ismanufactured on a silicon substrate. As understood by a person skilledin the art, other substrates such as GaN, Al₂O₃ (sapphire) and SiC alsocan implement a similar structure.

As shown in FIG. 5A to FIG. 5Z, a manufacturing method for a HEMT 500includes: at step 5001, as shown in FIG. 5A, a Si substrate 501 isprovided.

At step 5002, a plurality of first trenches are formed on the substrate,as shown in FIG. 5B. For example, the substrate 501 is etched by using alithography technology to form a plurality of rectangular first trenches521 on the substrate 501, and vertical interfaces 541 and 542 of thesubstrate 501 are exposed, where the substrate vertical interfaces 541and 542 in the first trenches 521 are (111) surfaces of the Si substrate(i.e., crystal <0001> surfaces). The first trenches 521 may also beobtained by other modes in the art, and these methods can also beapplied here.

In some embodiments, the number of the first trenches configured on asame substrate depends on specific requirements on an integration level,voltage withstanding and the like. The following take merely threetrenches as an example for description. According the method involved inthe present invention, the shape and size of the trenches can beconfigured in advance according to actual requirements, for example,when a semiconductor device having high voltage withstanding is formed,the depth of trenches is deep.

In some embodiments, when the exposed vertical interfaces are <000-1>surfaces, the HHMT as shown in FIG. 3 or FIG. 4 is formed. The detailsare not repeated here.

At step 5003, a protective layer is formed on the surfaces of thesubstrate and the first trenches on the substrate, as shown in FIG. 5C.A SiN protective layer 531 is grown on the substrate 501 by usingtechnologies such as LPCVD, covering the surfaces of the substrate 501and the plurality of trenches 521.

At step 5004, the protective layer horizontally extending on the bottomsof the first trenches and the upper surface of the substrate is removed,and the protective layers on sidewalls of the first trenches arereserved, as shown in FIG. 5D. By using the etching technology having avertical alignment, only the protective layers 531 formed by SiN on thevertical interfaces 541 and 542 are reserved, and the Si substrate 501on the bottoms of the trenches 521 is exposed. The protective layer 531covers the substrate vertical interfaces 541 and 542 of the trenches 521of the substrate.

At step 5005, first separation layers are formed on the substrate andthe first trenches, as shown in FIG. 5E. The separation layers 511 coverthe bottoms of the first trenches 521. In some embodiments, SiO₂ may beformed by an oxidation technology, such that the first separation layers511 are formed on the substrate 501. Because the vertical interfaces 541and 542 of the substrate 501 are covered with the protective layers 531,substantially no separation layer 511 is grown on the verticalinterfaces 541 and 542 of the substrate 501.

At step 5006, the protective layers on the sidewalls of the trenches areremoved, as shown in FIG. 5F. The separation layers 511 above thesubstrate 501 are covered by a mask, and then the protective layers 531on the sidewalls of the first trenches 521 are partially etched byselectively using an etching technology, the lithography technology orother technologies. For example, the etching may include removing partof the sidewalls of the first trenches 521. After etching, the verticalinterfaces 541 and 542 of the substrate 501 are exposed. There are othermethods in the art for removing the protective layers and exposing thevertical interfaces of the substrate. These methods can also be appliedhere.

At step 5007, a first nucleation layer and a second nucleation layer areformed on the vertical interfaces, as shown in FIG. 5G. The firstnucleation layer 502A and the second nucleation layer 502B are grown onthe exposed vertical surfaces 541 and 542 of the substrate 501. Thenucleation layers 502A and 502B includes AlN. In some embodiments, afterAlN is formed, one or more buffer materials in AIN, GaN, AlGaN, InGaN,AlInN and AlGaInN are further grown. In some embodiments, while thenucleation layers extend and grow horizontally, the nucleation layersalso grow vertically (not shown). By control process parameters, thenucleation layers are controlled to grow horizontally as much aspossible. Although growing in vertical direction is present, the devicestructure is not affected.

In some embodiments, nitride semiconductor nucleation layers (acomposite structure of AlN or AlN/AlGaN/GaN) are deposited, and becauseof low selectivity of Al growth, polycrystalline or amorphous AlN orAlGaN may exist on SiO₂. A wafer is taken out after the nucleationlayers are formed, and the polycrystalline or amorphous AlN or AlGaN isremoved by means of vertical etching.

At step 5008, a second separation layer is formed on the substrate ofthe entire device, as shown in FIG. 5H. On the structure as shown inFIG. 5G, a SiO₂ second separation layer 519 is formed by a depositionprocess. The trenches 521 are filled by the second separation layer 519,and the SiO₂ second separation layer 519 having a certain height isformed on the substrate. In some embodiments, if a semiconductor devicehaving a greater aspect ratio is intended to be formed, the height ofthe second separation layer 519 is increased accordingly.

At step 5009, the second separation layer is patterned to form aplurality of second trenches, so as to expose part of the nucleationlayers, as shown in FIG. 5I. By using the vertical etching technology,the second trenches 525 and 524 are vertically etched on the secondseparation layer 519. Basically, the second trenches 525 and 524 definethe height of a second layer of the semiconductor device, that is, theoverall height of the device after the device is formed. Moreover, theheight of the nucleation layer is restricted to the first layer. Theupper surfaces of the nucleation layers 502A and 502B are exposed on thebottoms of the trenches 523 and 524.

A person skilled in the art should note that the nucleation layers 502Aand 502B are formed on the Si substrate (111) surface, and therefore,the nucleation layers 502A and 502B have hexagonal symmetry. After theupper surfaces of the nucleation layers 502A and 502B are exposed, otherstructures formed in the trenches 523 and 524 also have hexagonalsymmetry.

At step 5010, first ohmic contact doped regions are grown in theplurality of second trenches, as shown in FIG. 5J. The nitridesemiconductor and a doping medium are deposited on the nucleation layers502A and 502B by means of chemical vapor doping, to form the first ohmiccontact doped regions 531A and 531B. For a device implementingconduction by 2DEG, the doping type is N type. For a device implementingconduction by 2DHG, the doping type is P type. Because carriers in the2DEG are electrons, N-type doping also implements conduction byelectrons. Therefore, it can be considered that the doping type is thesame as a two-dimensional carrier type. For conventional deposition orepitaxial growth, the growth condition thereof in the horizontaldirection cannot be easily controlled, and therefore, it is difficultfor the semiconductor structure to keep growing completely vertically,and a plurality of growth surfaces may be formed. The structure involvedin the present invention can keep continuous growth on a same surface,and improve the electrical characteristics of the device.

At step 5011, first channel regions are formed on the first ohmiccontact doped regions, as shown in FIG. 5K. The nitride semiconductorand a doping medium are deposited on the first ohmic contact dopedregions 531A and 531B by means of chemical vapor doping, to form thefirst channel region 532A and the third channel region 532B. Doping ofthe first channel region 532A and the third channel region 532B islow-doping or non-(intentional) doping, and the doping type is N type.

At step 5012, electric field modulation doped regions are formed on thefirst channel regions, as shown in FIG. 5L. The nitride semiconductorand a doping medium are deposited on the first channel region 532A andthe third channel region 532B by means of chemical vapor doping, to formthe electric field modulation doped regions 533A and 533B. Doping typesof the electric field modulation doped regions 533A and 533B are P type.

At step 5013, gate stack doped regions are formed on the electric fieldmodulation doped regions, as shown in FIG. 5M. The nitride semiconductorand a doping medium are introduced on the electric field modulationdoped regions 533A and 533B by means of chemical vapor doping, to formthe gate doped regions 534A and 534B. Doping types of the gate dopedregions 534A and 534B are P type, and the doping concentrations of thegate doped regions 534A and 534B are higher than those of the electricfield modulation doped regions 533A and 533B.

At step 5014, second channel regions are formed on the gate dopedregions, as shown in FIG. 5N. The nitride semiconductor and a dopingmedium are introduced on the gate doped regions 534A and 534B by meansof chemical vapor doping, to form the second channel region 535A andfourth channel regions 535B. Doping of the second channel region 535Aand the fourth channel regions 535B is low-doping or non-(intentional)doping, and the doping type is N type.

At step 5015, second ohmic contact doped regions are formed on thesecond channel regions and the fourth channel regions, as shown in FIG.5O. The nitride semiconductor and a doping medium are introduced on thesecond channel regions and the fourth channel regions 535A and 535B bymeans of chemical vapor doping, to form the second ohmic contact dopedregions 536A and 536B. Doping types of the second ohmic contact dopedregions 536A and 536B are N type.

At step 5016, the remaining second separation layer is removed, as shownin FIG. 5P. The remaining second separation layer 519 is removed byusing the etching technology. After removal, the upper surfaces of theseparation layers 511 are exposed, and a first channel layer and asecond channel layer, except the positions in contact with thenucleation layers, are all exposed. The positions in contact with thefirst channel layers and the second channel layers and the sidewalls notin contact with the substrate on the upper surfaces of the nucleationlayers are exposed.

At step 5017, a barrier layer is deposited, as shown in FIG. 5Q. Thebarrier layer 504 is deposited on the device, and the barrier layercovers the surface of the device. The barrier layer 504 is formed, wherea first heterojunction and a second heterojunction both having avertical interface are formed between the first channel layer and thefirst barrier layer, and vertical 2DEG 505A and 2DHG 505B are formed inthe first heterojunction and the second heterojunction. Similarly, athird heterojunction and a fourth heterojunction both having a verticalinterface are formed between the second channel layer and the firstbarrier layer, and vertical 2DEG 505C and 505D is formed in the thirdheterojunction and the fourth heterojunction. In some embodiments, arelatively thin non-doped channel layer is first deposited before thebarrier layer is deposited, and the material of the channel layer is thesame as that of the nitride semiconductor of the substrate of theoriginal channel layer. This can ensure good contact between the barrierlayer and the channel layer, and the electrical characteristics are morestable.

At step 5018, an insulating layer is deposited, as shown in FIG. 5R. Theinsulating layer 518 is deposited on the surface of the device, theinsulating layer 518 covers the barrier layer 504, and finally thedevice becomes flatter.

At step 5019, the insulating layer is patterned, and third trenches areformed between the first channel layer and the second channel layer, asshown in FIG. 5S. In some embodiments, the insulating layer 518 isetched between the first channel layer and the second channel layer, toform third trenches 525, and moreover, the reserved insulating layerforms a shielding layer 512. The etching depth here needs to be ensuredto be slightly lower than the contact surfaces between the gate dopedsurfaces and the electric field modulation doped regions, to ensure goodcontact between electrodes and the gate doped regions in a subsequentelectrode formation process.

At step 5020, third electrodes are deposited, as shown in FIG. 5T. Thethird electrodes 509 are configured at the bottoms of the trenches 525,between first gate doped regions and second gate doped regions, and inelectric contact with the 2DEG 505A and 505B in the firstheterojunction. The third electrodes 509 are formed between the barrierlayers by means of electrode deposition. To ensure full electric contactof the third electrodes 509 with the first gate doped regions and thesecond gate doped regions, the height of the electrodes 509 is slightlyhigher than the upper surfaces of the first gate doped regions and thesecond gate doped regions. In some embodiments, the electrodes 509 arepositioned closer to an upper position as a gate. The electrodes 509, asa gate, being positioned as far away from a drain as possible improvesthe overall voltage withstanding of the device. In some embodiments, theelectrodes 509 may be two electrodes respectively controlling the firstchannel layer and the second channel layer. The process in the solutionof the present embodiment is simpler.

At step 5021, a third separation layer is deposited, and then the uppersurfaces of the first channel layer and the second channel layer areexposed, as shown in FIG. 5U. The third separation layer 514 is formedon the entire device again. SiO₂ is deposited on the semiconductordevice by using a deposition process, to make SiO₂ fill the part aboveelectrodes 507 and cover the channel layers and the barrier layers,thereby forming the third separation layer 514. Then, part of thebarrier layer 504 is removed by using a lithography process to exposethe upper surfaces of the first channel layer and the second channellayer. At this time, the barrier layer 504, which is originally as awhole, is separated into a first barrier layer 504A, a second barrierlayer 504B, a third barrier layer 504C and a fourth barrier layer 504D.

At step 5022, second electrodes are deposited, as shown in FIG. 5V. Thesecond electrodes 508A and 508B are formed by using the electrodedeposition method at positions on the upper surfaces of the firstchannel layer and the second channel layer and close to the 2DEG 505Aand 505B. The second electrodes 508A and 508B are in ohmic contact withthe second ohmic contact doped regions, and electrically connected tothe 2DEG 505A and 505C. Moreover, the second electrodes 508A and 508Bare not electrically connected to the 2DHG 505B and 505D. In someembodiments, the second electrodes 508A and 508B serve as a source ofthe device. In some embodiments, the second electrodes 508A and 508B areconnected to a low level, e.g., 0 V.

In some embodiments, the second electrodes 508A and 508B may also be asame electrode.

At step 5023, the insulating layer close to the second barrier layer andthe fourth barrier layer is patterned, as shown in FIG. 5W. By using thevertical etching technology, part of the insulating layer 518 of thesecond barrier layer and the fourth barrier layer is etched to formtrenches 526. Meanwhile, an insulating layer 513 is formed. The etchingdepth here needs to be ensured to be slightly lower than the contactsurfaces between the gate doped surfaces and the electric fieldmodulation doped regions, to ensure good contact between electrodes andthe gate doped regions in a subsequent electrode formation process.

At step 5024, fourth electrodes are deposited, as shown in FIG. 5X. Thefourth electrodes 506 are configured at the bottoms of the trenches 526,between the first gate doped regions and the second gate doped regions,and in electric contact with the 2DHG 505B and 505D in the firstheterojunction. The fourth electrodes 506 are formed between the barrierlayers by means of electrode deposition. To ensure full electric contactof the fourth electrodes 506 with the first gate doped regions and thesecond gate doped regions, the height of the electrodes 506 is slightlyhigher than the upper surfaces of the first gate doped regions and thesecond gate doped regions. In some embodiments, the electrodes 506 areconfigured, as body electrodes, at positions having the same height ofthe electrodes 509. In some embodiments, the electrodes 506 may be twoelectrodes respectively controlling the first channel layer and thesecond channel layer. The process in the solution of the presentembodiment is simpler. The fourth electrodes in direct ohmic contactwith the 2DHG may also be formed, and moreover, the fourth electrodesare electrically connected to the gate doped regions by means of the2DHG.

At step 5025, the entire semiconductor device is turned over, and thesubstrate and the nucleation layers are removed, as shown in FIG. 5Y. Asshown in FIG. 5Y, after the semiconductor device is turned over, thesubstrate 501 is oriented upwards. The substrate 501 is first thinned,and then, by means of wet etching, the entire substrate 501 and thenucleation layers 502A and 502B are removed from the semiconductordevice. The upper surfaces of the first channel layer and the secondchannel layer are exposed.

At step 5026, first electrodes are deposited, as shown in FIG. 5Z. Bymeans of metal deposition, metal electrodes, i.e., the first electrodes507, are formed on the first channel layer and the second channel layer.The first electrodes 507 are electrically connected to both the 2DEG505A and 505C in the first heterojunction and the third heterojunction,but are not electrically connected to the 2DHG 505B and 505D.

In some embodiments, the subsequent steps includes forming a firstconductor interconnecting layer, a second conductor interconnectinglayer and a third conductor interconnecting layer, which areelectrically connected to the first electrodes, the second electrodesand the third electrodes, respectively. These steps are all well knownby a person skilled in the art and is not repeated here.

The channel layers of the HEMT formed by the foregoing method haverelatively high aspect ratios. Moreover, the device is normally off in anon-energized state.

The foregoing structure of the present invention merely exemplarilydescribes the technical solution of the present invention. In someembodiments, a same trench may include more semiconductor structures,thereby achieving a solution having a higher integration level. Forexample, when the HHMT is formed, it is merely required to adjust thecrystal orientation of the vertical interfaces of the substrate and thedoping types in various regions in the channel layers.

The above-described embodiments are merely illustrative of the presentinvention, and are not intended to limit the present invention. Variouschanges and modifications may also be made by persons of ordinary skillin the art without departing from the scope of the present invention.Therefore, all the equivalent technical solutions should also fallwithin the scope of the present invention.

1. A semiconductor device, comprising: a first channel layer, whichcomprises a first channel region, a first gate doped region, and asecond channel region, wherein the second channel region is locatedabove the first channel region, and the first gate doped region islocated between the first channel region and the second channel region;a first barrier layer, wherein a first heterojunction having a verticalinterface is formed between the first channel layer and the firstbarrier layer, and a vertical 2DEG or 2DHG is formed in the firstheterojunction; a first electrode, which is located below the first gatedoped region and in electric contact with the 2DEG or 2DHG in the firstheterojunction; a second electrode, which is located above the firstgate doped region and in electric contact with the 2DEG or 2DHG in thefirst heterojunction; and a third electrode, which is in electriccontact, in the first gate doped region, with the 2DEG or 2DHG in thefirst heterojunction.
 2. The semiconductor device according to claim 1,wherein a doping type of the first gate doped region is opposite to atwo-dimensional carrier type in the first heterojunction.
 3. Thesemiconductor device according to claim 1, wherein the first gate dopedregion depletes two-dimensional carriers in the first heterojunction. 4.The semiconductor device according to claim 1, wherein the first channellayer comprises a first electric field modulation doped region, whereinthe first electric field modulation doped region is electricallyconnected to the first gate doped region.
 5. The semiconductor deviceaccording to claim 4, wherein the first electric field modulation dopedregion is located near the third electrode.
 6. The semiconductor deviceaccording to claim 4, wherein the first electric field modulation dopedregion is located between the first electrode and the third electrode.7. The semiconductor device according to claim 1, wherein the firstchannel region of the first channel layer is lowly doped ornon-intentionally doped.
 8. The semiconductor device according to claim1, wherein the first channel region of the second channel layer is lowlydoped or non-intentionally doped.
 9. The semiconductor device accordingto claim 1, wherein the first channel layer comprises a first ohmiccontact doped region adjacent to the first electrode.
 10. Thesemiconductor device according to claim 1, wherein the first channellayer comprises a second ohmic contact doped region adjacent to thesecond electrode.
 11. The semiconductor device according to claim 1,further comprising a second barrier layer, wherein a secondheterojunction having a vertical interface is formed between the firstchannel layer and the second barrier layer, and a vertical 2DEG or 2DHGis formed in the second heterojunction.
 12. The semiconductor deviceaccording to claim 11, further comprising a fourth electrode, which isin electric contact with the first gate doped region.
 13. Thesemiconductor device according to claim 12, wherein the fourth electrodeindependently controls or is electrically connected to the firstelectrode.
 14. The semiconductor device according to claim 12, whereinthe second barrier layer is located below the fourth electrode.
 15. Thesemiconductor device according to claim 1, further comprising a firstnucleation layer, wherein the first channel layer is epitaxially grownfrom the first nucleation layer.
 16. The semiconductor device accordingto claim 15, wherein the first channel layer is located above the firstnucleation layer.
 17. The semiconductor device according to claim 15,wherein the first nucleation layer is doped.
 18. The semiconductordevice according to claim 15, wherein the first nucleation layer isepitaxially grown from a first vertical interface of a substrate. 19.The semiconductor device according to claim 1, wherein the first channellayer is defined by a trench.
 20. The semiconductor device according toclaim 1, wherein the first electrode is connected to a first externalvoltage below the first heterojunction, and the second electrode isconnected to a second external voltage above the first heterojunction.21. The semiconductor device according to claim 1, further comprising: asecond channel layer, which comprises a third channel region, a secondgate doped region, and a fourth channel region, wherein the fourthchannel region is located above the third channel region, and the secondgate doped region is located between the third channel region and thefourth channel region; a third barrier layer, wherein a thirdheterojunction having a vertical interface is formed between the secondchannel layer and the third barrier layer, and a vertical 2DEG or 2DHGis formed in the third heterojunction; a fifth electrode, which islocated below the second gate doped region and in electric contact withthe 2DEG or 2DHG in the third heterojunction; and a sixth electrode,which is located above the second gate doped region and in electriccontact with the 2DEG or 2DHG in the third heterojunction; wherein thethird electrode is in electric contact, in the second gate doped region,with the 2DEG or 2DHG in the third heterojunction.
 22. The semiconductordevice according to claim 21, wherein the first electrode and the fifthelectrode are a same electrode.
 23. The semiconductor device accordingto claim 21, wherein the second electrode and the sixth electrode are asame electrode.
 24. The semiconductor device according to claim 21,wherein the second channel layer comprises a second electric fieldmodulation doped region, wherein the second electric field modulationdoped region is electrically connected to the second gate doped region.25. The semiconductor device according to claim 21, further comprising afourth barrier layer, wherein a fourth heterojunction having a verticalinterface is formed between the second channel layer and the fourthbarrier layer, and a vertical 2DEG or 2DHG is formed in the fourthheterojunction.
 26. The semiconductor device according to claim 24,further comprising a seventh electrode, which is in electric contact, inthe second gate doped region, with the 2DEG or 2DHG in the fourthheterojunction.
 27. The semiconductor device according to claim 25,wherein the seventh electrode independently controls or is electricallyconnected to the fifth electrode.
 28. The semiconductor device accordingto claim 21, further comprising a second nucleation layer, wherein thesecond channel layer is epitaxially grown from the second nucleationlayer.
 29. The semiconductor device according to claim 27, wherein thesecond nucleation layer is epitaxially grown from a second verticalinterface of a substrate.
 30. The semiconductor device according toclaim 21, further comprising a foreign substrate. 31-40. (canceled)